Phase locked loop (PLL) circuits have been used in wireless devices, optical transmission devices and other devices for mobile communication, video transmission, digital TV broadcasting and other purposes to produce stable output of wide-band frequency signals. For example, in a wireless communication technology applied to mobile phones, personal handyphone systems (PHS) or wireless local area networks (LAN), data is carried on a carrier of a frequency oscillated by the PLL circuit to form radio waves, which are transmitted and received to establish communications.
In the wireless communication technology, multiple lines of data may be accurately transmitted and received while the PLL circuit properly changing frequencies of the carrier. Hereinafter, an exemplary related art PLL circuit will be described with reference to FIG. 8. As illustrated in FIG. 8, the PLL circuit includes a phase comparator, a loop filter, a voltage controlled oscillator (VCO) and a feedback frequency divider.
The PLL circuit synchronizes a phase of a signal self-oscillated by the VCO to a phase of REFCLK, which is a PLL input reference signal, and outputs a signal following REFCLK (“PLL output”). In particular, a phase comparator compares a phase of REFCLK with a phase of FBCLK which is a signal oscillated by the VCO and outputs a phase difference between REFCLK and FBCLK to a loop filter as a difference signal. The loop filter filters the difference signal input from the phase comparator and outputs the filtered difference signal to the VCO. The VCO oscillates at a frequency determined in accordance with the difference signal output from the phase comparator via the loop filter and outputs a signal. The loop filter illustrated in FIG. 8 is a low pass filter (LPF) which filters out high-frequency components in the input signal.
The frequency of the signal oscillated by the VCO is divided by feedback frequency divider by a predetermined frequency division ratio and the frequency divided signal is output as FBCLK to the phase comparator. As a result, the PLL circuit may output a signal of a frequency as the frequency division ratio times the frequency of REFCLK. In this manner, the PLL circuit can output a frequency-divided or frequency-multiplied signal of REFCLK. That is, the PLL circuit generates various frequencies in synchronization with the input signal REFCLK to thereby enable accurate transmission and reception of multiple lines of data.
In recent years, there have been disclosed a PLL circuit which reduces phase errors between the reference signal REFCLK and the frequency-divided signal FBCLK (for example, Japanese Laid-open Patent Publication No. 08-162948) and a PLL circuit which rapidly switches output frequencies without a loop filter have been developed (for example Japanese Laid-open Patent Publication No. 05-90962).